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| EliteMT DRAM M10B416256A 256 K x 16 DRAM FAST PAGE MODE FEATURES Y Y Y Y Y Y Y Y Y X16 organization FAST PAGE access mode 2 CAS Byte/Word Read/Write operation Single 5V ( 10%) power supply TTL-compatible inputs and outputs 512-cycle refresh in 8ms Refresh modes : RAS only, CAS BEFORE RAS (CBR) and HIDDEN JEDEC standard pinout Key AC Parameter tRAC -50 -60 50 60 tCAC 13 15 tRC 84 104 tPC 26 29 ORDERING INFORMATION - PACKAGE 40-pin 400mil SOJ 44 / 40-pin 400mil TSOP (TypeII) PRODUCT NO. M10B416256A-50J/60J M10B416256A-50T/60T PACKING TYPE SOJ TSOPII GENERAL DESCRIPTION The M10B416256A is a randomly accessed solid state memory, organized as 262,144 x 16 bits device. It offers FAST Page Mode, 5V( 10%) single power supply. Access time (-50, -60) and package type (SOJ, TSOP II) are optional features of this family. All these family have CAS - before - RAS , RAS -only refresh and Hidden refresh capabilities. Two access modes are supported by this device : Byte access and Word access. Use only one of the two CAS and leave the other staying high will result in a BYTE access. WORD access happens when two CAS ( CASL , CASH ) are used. CASL transiting low during READ or WRITE cycle will output or input data into the lower byte (IO0~IO7), and CASH transiting low will output or input data into the upper byte (IO8~15). PIN ASSIGNMENT SOJ Top View VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC NC WE RA S NC A0 A1 A2 A3 VCC TSOP (TypeII) Top View VS S I/O1 5 I/O1 4 I/O1 3 I/O1 2 VS S I/O1 1 I/O1 0 I/O9 I/O8 NC CA SL C ASH OE A8 A7 A6 A5 A4 VSS VC C I/O 0 I/O 1 I/O 2 I/O 3 VC C I/O 4 I/O 5 I/O 6 I/O 7 NC NC WE RA S NC A0 A1 A2 A3 VC C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 V SS I/O 15 I/O 14 I/O 13 I/O 12 V SS I/O 11 I/O 10 I/O 9 I/O 8 NC C AS L C AS H OE A8 A7 A6 A5 A4 V SS Elite Memory Technology Inc Publication Date : Dec. 2000 Revision : 1.2 1/15 EliteMT FUNCTIONAL BLOCK DIAGRAM M10B416256A WE RAS CASL CASH CONTROL LOGIC DATA-IN BUFFER 16 IO0 : IO15 CLOCK GENERATOR DATA-OUT BUFFER 9 COLUMN DECODER 512 16 OE 16 9 A0 A1 A2 A3 COLUMN ADDRESS BUFFER REFRESH CONTROLER SENSE AMPLIFIERS I/O GATING 8 512 x 16 A4 A5 A6 A7 A8 9 99 ROW. ADDRESS BUFFERS(9) 9 ROW DECODER 512 x 512 x 16 MEMORY ARRAY REFRESH COUNTER 512 VBB GENERATOR VCC VSS PIN DESCRIPTIONS PIN NO. 16~19,22~26 14 28 29 13 27 2~5,7~10,31~34,36~39 1,6,20 21,35,40 11,12,15,30 PIN NAME A0~A8 RAS CASH CASL WE OE TYPE Input Input Input Input Input Input Input / Output Supply Ground - DESCRIPTION Address Input Row Address : A0~A8 Column Address : A0~A8 Row Address Strobe Column Address Strobe / Upper Byte Control Column Address Strobe / Lower Byte Control Write Enable Output Enable Data Input / Output Power, 5V Ground No Connect I/O0 ~ I/O15 VCC VSS NC Elite Memory Technology Inc Publication Date : Dec. 2000 Revision : 1.2 2/15 EliteMT ABSOLUTE MAXIMUM RATINGS Voltage on Any pin Relative to Vss ... ...... -1V to +7V Operating Temperature, TA (ambient) ... C to +70 C .0 Storage Temperature (plastic) ......... .-55 C to +150 C Power Dissipation ....................................... 0.8W Short Circuit Output Current ........................ 50mA M10B416256A Permanent device damage may occur if "Absolute Maximum Ratings" are exceeded. This is a stress rating only, and functional operation of the device above those conditions indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (0 C TA 70 C ; VCC = 5V 10% unless otherwise noted) PARAMETER Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Note : 1.All Voltages referenced to VSS 0V VIH 7V 0V VOUT 7V Output(s) disable IOH = -5 mA IOL = 4.2 mA CONDITIONS SYMBOL VCC VSS VIH VIL ILI ILO VOH VOL MIN 4.5 0 2.4 -1.0 -10 -10 2.4 MAX 5.5 0 VCC +1 0.8 10 10 0.4 UNITS NOTES V V V V A A V V 1 1 1 PARAMETER Operating Current Standby Current CONDITIONS RAS , CAS cycling , tRC =min SYMBOL ICC1 ICC2 MAX -50 130 4 2 -60 110 4 2 110 110 5 110 UNITS NOTES mA mA mA mA mA mA mA 1,2 TTL interface , RAS , CAS = VIH , DOUT =High-Z CMOS interface, RAS , CAS VCC-0.2V RAS only refresh Current tRC = min tPC = min RAS =VIH, CAS = VIL ICC3 ICC4 ICC5 ICC6 130 130 5 130 2 1,3 1 FAST Page Mode Current Standby Current CAS Before RAS Refresh Current tRC = min Note : 1. ICC max is specified at the output open condition. 2. Address can be changed twice or less while RAS =VIL . 3. Address can be changed once or less while CAS =VIH . Elite Memory Technology Inc Publication Date : Dec. 2000 Revision : 1.2 3/15 EliteMT CAPACITANCE (Ta = 25 C , VCC = 5V 10%) PARAMETER Input Capacitance (address) Input Capacitance ( RAS , CASH , CASL , WE , OE ) Output capacitance (I/O0~I/O15) SYMBOL CI1 CI2 CI / O TYP MAX 5 7 10 M10B416256A UNIT pF pF pF AC ELECTRICAL CHARACTERISTICS (Ta = 0 to 70 C , VCC =5V 10%, VSS = 0V) (note 14) Test Conditions Input timing reference levels : 0V, 3V Output reference level : VOL= 0.8V, VOH=2.0V Output Load : 2TTL gate + CL (50pF) Assumed tT = 2ns PARAMETER Read or Write Cycle Time Read Write Cycle Time Fast-Page-Mode Read or Write Cycle Time Fast-Page-Mode Read-Write Cycle Time Access Time From RAS Access Time From CAS Access Time From OE Access Time From Column Address Access Time From CAS Precharge RAS Pulse Width RAS Pulse Width (Fast Page Mode) RAS Hold Time RAS Precharge Time CAS Pulse Width CAS Hold Time CAS Precharge Time RAS to CAS Delay Time CAS to RAS Precharge Time SYMBOL tRC tRWC tPC tPCM tRAC tCAC tOAC tAA tACP tRAS tRASC tRSH tRP tCAS tCSH tCP tRCD tCRP tASR tRAH tRAD tASC tCAH tAR tRAL -50 MIN 84 116 26 60 50 13 13 25 24 50 50 13 30 13 50 7 11 5 0 7 9 0 7 40 25 25 37 10K 10K 100K -60 MAX MIN 104 140 29 70 60 15 15 30 27 60 60 15 40 15 60 10 14 5 0 10 12 0 10 50 30 30 45 10K 10K 100K MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes 22 22 4 5,20 13,20 20 24 19 23 7,18 19 Row Address Setup Time Row Address Hold Time RAS to Column Address Delay Time 8 18 18 Column Address Setup Time Column Address Hold Time Column Address Hold Time (Reference to RAS ) Column Address to RAS Lead Time Elite Memory Technology Inc Publication Date : Dec. 2000 Revision : 1.2 4/15 EliteMT (Continued) -50 PARAMETER Read Command Setup Time Read Command Hold Time Reference to CAS Read Command Hold Time Reference to RAS CAS to Output in Low-Z M10B416256A -60 MAX MIN MAX SYMBOL tRCS tRCH tRRH tCLZ tOFF1 tOFF2 tWCS tWCH tWCR tWP tRWL tCWL tDS tDH tDHR tRWD tAWD tCWD tT tREF tRPC tCSR tCHR tOEH tORD tCLCH tRSR tRHR MIN UNIT ns ns ns ns Notes 15,18 9,15,19 9 20 10,17,20 17,25 11,15,18 15,24 15 15 15 15,19 12,20 12,20 0 0 0 3 3 15 8 0 7 40 7 13 9 0 7 40 67 42 30 1 10 10 10 7 0 13 5 5 50 8 0 0 0 3 3 15 8 0 10 50 10 15 10 0 10 50 79 49 34 1 10 10 10 10 0 15 5 5 50 8 Output Buffer Turn-off Delay From CAS or RAS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns Output Buffer Turn-off to OE Write Command Setup Time Write Command Hold Time Write Command Hold Time(Reference to RAS ) Write Command Pulse Width Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Setup Time Data-in Hold Time Data-in Hold Time (Reference to RAS ) RAS to WE Delay Time 11 11 11,18 2,3 Column Address to WE Delay Time CAS to WE Delay Time Transition Time (rise or fall) Refresh Period (512 cycles) RAS to CAS Precharge Time CAS Setup Time(CBR REFRESH) CAS Hold Time(CBR REFRESH) OE Hold Time From WE During Read-ModeWrite Cycle OE Setup Prior to RAS During Hidden Refresh Cycle 1,18 1,19 16 Last CAS Going Low to First CAS Returning High Read Setup Time Reference to RAS in CBR Read Hold Time Reference to RAS in CBR 21 Elite Memory Technology Inc Publication Date : Dec. 2000 Revision : 1.2 5/15 EliteMT Notes : 1. 2. Enables on-chip refresh and address counters. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL. In addition to meet the transition rate specification, all input signals must transit between VIH and VIL in a monotonic manner. Assume that tRCD < tRCD(max). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCD exceeds the value shown. Assume that tRCD tRCD (max) If CAS is low at the falling edge of RAS , data-out will be maintained from the previous cycle. To initiate a new cycle and clear the data-out buffer, CAS and RAS must be pulsed high. M10B416256A back to VIH ) is indeterminate. OE held high and WE taken low after CAS goes low result in a LATE WRITE ( OE -controlled) cycle. 12. Those parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ-MODIFY- WRITE cycles. 13. During a READ cycle, if OE is low then taken HIGH before CAS goes high, I/O goes open, if OE is tied permanently low, a LATE WRITE or READ-MODIFYWRITE operation is not possible. An initial pause of 100ms is required after power-up followed by eight RAS refresh cycles ( RAS only or CBR) before proper device operation is assured. The eight RAS cycle wake-ups should be repeated any time the tREF refresh requirement is exceeded. WRITE command is defined as WE going low. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOFF2 and tOEH met ( OE high during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycles. The I/Os open during READ cycles once tOFF1 or tOFF2 occur. Referenced to the earlier CAS falling edge. 3. 4. 5. 6. 14. 7. 8. 9. 10. 11. Operation within the tRCD limit ensures that tRCD (max) can be met, tRCD (max) is specified as a reference point only ; if tRCD is greater than the specified tRCD (max) limit, access time is controlled by tCAC. Operation within the tRAD limit ensures that tRAD(max) can be met. tRAD(max) is specified as a reference point only ; if tRAD is greater than the specified tRAD (max) limit, access time is controlled by tAA. Either tRCH or tRRH must be satisfied for a READ cycle. tOFF1(max) defines the time at which the output achieves the open circuit condition ; it is not a reference to VOH or VOL. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFYWRITE cycle only. If tWCS tWCS(min) , the cycle is an EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. If tRWD tRWD(min) , tAWD tAWD(min) and tCWD tCWD(min) , the cycle is READ-WRITE and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go 15. 16. 17. 18. 19. Referenced to the latter CAS rising edge. 20. Output parameter (I/O) is referenced to corresponding CAS input, IO0~7 by CASL and IO8~15 by CASH . 21. Last falling CAS edge to first rising CAS edge. 22. Last rising CAS edge to next cycle' s last rising CAS edge. 23. Last rising CAS edge to first falling CAS edge. 24. Referenced to the latter CAS falling edge. 25. All IOs controlled by OE , regardless CASL and CASH . Elite Memory Technology Inc Publication Date : Dec. 2000 Revision : 1.2 6/15 EliteMT TRUTH TABLE ADDRESSES RAS CASL CASH M10B416256A FUNCTION Standby Read : Word Read : Lower Byte Read : Upper Byte Write : Word (Early Write) Write : Lower Byte (Early) WE X H H H L L OE ROW X ROW ROW ROW ROW ROW COL X COL COL COL COL COL High-Z Data-Out DQS NOTES H L L L L L HaX L L H L L HaX L H L L H X L L L X X Lower Byte, Data-Out Upper Byte, Data-Out Data-In Lower Byte, Data-In , Upper Byte, High-Z Lower Byte, High-Z , Upper Byte, Data-In Data-Out, Data-In Data-Out Data-Out Data-In Data-In Data-Out, Data-In Data-Out, Data-In Data-Out High-Z 1, 2 2 2 1 1 1, 2 1, 2 2 Write : Upper Byte (Early) Read-Write Fast-Page-Mode 1st Cycle Read 2nd Cycle Fast-Page-Mode 1st Cycle Write 2nd Cycle Fast-Page-Mode 1st Cycle Read-Write 2nd Cycle Hidden Refresh RAS -Only Refresh L L L L L L L L LaHaL L HaL H L HaL HaL HaL HaL HaL HaL L H L L L HaL HaL HaL HaL HaL HaL L H L L X ROW ROW ROW COL COL COL COL HaL LaH H H L L L L X X ROW COL COL HaL LaH HaL LaH H X H L X X ROW COL COL ROW ROW X COL CBR Refresh X High-Z 3 *Note : 1. These WRITE cycles may also be BYTE WRITE cycles (either CASL or CASH active). 2. These READ cycles may also be BYTE READ cycles (either CASL or CASH active). 3. Only one CAS must be active ( CASL or CASH ). Elite Memory Technology Inc Publication Date : Dec. 2000 Revision : 1.2 7/15 EliteMT READ CYCLE tR C tRAS RAS VI H VIL M10B416256A tRP tC RP VIH C A S L , C AS H V I L tRC D tCS H tR S H tC AS, tC LC H tRRH tAR tRAD tASR AD DR VIH VIL ROW tRAH tAS C tRAL tCAH COLUMN ROW tR CS WE VIH VIL tRCH tAA tRAC tCAC tCLZ I/ O VOH VOL OPEN O AC tOFF1 VALID DATA O PE N tO F2 OE VIH VIL EARLY WRITE CYCLE VIH VIL tR C tRAS tRP tCS H RAS tCRP CASL,CASH VIH VIL tRC D tRS H tC AS ,tC LC H tAR tASR tRAD tRAH ROW tRAL tAS C tCAH COL UMN ROW AD DR VIH VIL tC W L tR W L tW C R tWCH tWP WE VIH VIL tWCS tDH R tDS I/ O VIH VIL VIH VIL tD H V AL I D D AT A OE DON'T CARE UNDEFINED Elite Memory Technology Inc Publication Date : Dec. 2000 Revision : 1.2 8/15 EliteMT READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE CYCLES) tRWC t RAS RA S VIH VIL M10B416256A tRP tCSH tRSH tCRP CASL ,C ASH VIH VIL tRCD tC AS , t CLC H t AS R ADDR VIH VIL ROW tAR t R AD t R AH t AS C tR AL tC AH CO LU M N ROW tRCS VIH VIL t RW D tCWD tAWD tCWL tRW L tWP WE tAA tR AC t C AC tCLZ VI / O H I/ O VI / O L O PE N VAL ID DO U T tDS tDH VALID DIN tOAC OE VIH VIL tOFF2 tOEH FAST-PAGE-MODE READ CYCLE tRASC RA S VIH VIL tRP tCSH tC R CASL,CASH VIH VIL tPC tRCD tC AS ,tCLC H t P t CA S,t CLC H tCP tRSH tC AS ,t C LC H t CP tAR t R AD tASR tRAH ADDR VI H VI L ROW t AS C t C AH t AS C tC AH t AS C t R AL t C AH ROW C OL UM N COLUMN C OL UM N tRCS tRCS WE VIH VIL tRCS tRCH tRCH tR R H tRCH tAA t RAC t CAC t CLZ I/ O VO H VO L OPEN VALID DATA tO F F 1 tCLZ tAA tACP t C AC tAA t AC P tO F F 1 tCLZ VA LID DATA VALID DATA t C AC tO F F 1 O PE N tO AC OE VIH VIL tO F F 2 tOAC tOFF2 t O AC tOFF2 DON'T CARE UNDEFINED Elite Memory Technology Inc Publication Date : Dec. 2000 Revision : 1.2 9/15 EliteMT FAST-PAGE-MODE EARLY-WRITE CYCLE tR AS C RAS VIH VIL M10B416256A tRP tCSH tC R P CASL ,C ASH VIH VIL tRCD tC AS , t C LCH tPC tCP tC AS , t CLC H t CP tRSH tCAS, tCLCH tCP tAR t R AD tASR AD DR VI H VI L t R AL tASC t CAH tASC tC AH tASC t C AH ROW t R AH ROW CO LUMN COLUMN COLUMN tWCS t CW L t W CH tWP tW CS tCW L tW CH tW P t W CS t CW L tWCH tW P WE VI H VI L tWCR tDHR t DS I/O VIH VIL tRWL tDS tDH tDS tDH tDH VALID DATA V AL ID D AT A VALID DATA OE VIH VIL FAST-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE CYCLES) t R AS C RA S VI H VI L tRP tCSH tCRP C A S L , C AS H VIH VIL tRCD tC AS , t C LCH tCP tPCM tC AS , t CLC H t CP tRSH tC AS , t C LCH tCP tAR t R AD t AS R ADDR VIH VIL t R AL tASC tC AH C OL UM N t R AH t AS C t CA H COLUMN t AS C t C AH ROW ROW C OL UM N tRW D tRCS tCWL tW P tA WD tCWD WE V V H L tR W t CW L tW P tAWD tCWD tAWD tCW D L tCW L tWP tAA t R AC t CAC tCLZ I/ O VI/OH VI/OL VA LI D VA LI D DOUT DIN tAA tDH tDS t AC P tC AC tCLZ VA LI D V A LI D DO UT DIN tAA tDH t DS t AC P t C AC tCLZ VA LI D VA LI D D IN DO UT tDH tDS tOFF2 tO AC OE VIH VIL tOFF2 t O AC t O AC tO F F 2 tOEH DON'T CARE UNDEFINED Elite Memory Technology Inc Publication Date : Dec. 2000 Revision : 1.2 10/15 EliteMT RAS ONLY REFRESH CYCLE (ADDR = A0~A8 ; OE , WE = DON' T CARE) tRC tRAS RAS VIH VIL M10B416256A tRP tCRP CA SL ,CAS H VIH VIL tRP C tASR ADDR V IH V IL R OW t R AH R OW I /O VOH VOL OP EN CBR REFRESH CYCLE (A0~A8 ; OE = DON' T CARE) tRP RAS VIH VIL t RA S t RP t R AS tRPC tCP C A SL , C AS H VIH VIL tCSR tCH R tRPC tCSR tCH R I/ O VO H VO L OPEN tRC H WE VIH VIL tRSR tR HR tR S R tRH R (NO TE1 ) D O N 'T CA R E UNDE FI NED Note : 1. tRSR and tRHR are for system design reference only. The WE signal is actually a "don' t care" at RAS time during a CBR REFRESH. However, WE should be held HIGH at RAS time during a CBR REFRESH to ensure compatibility with other DRAMs which require WE HIGH at RAS time during a CBR REFRESH. Elite Memory Technology Inc Publication Date : Dec. 2000 Revision : 1.2 11/15 EliteMT HIDDEN REFRESH CYCLE ( WE = HIGH ; OE = LOW) (READ) (RE F RE SH ) M10B416256A t R AS RAS V IH V IL t RP tRAS tCR P C ASL ,C AS H V IH V IL tRC D tRSH tCHR tA R tRAD tASR A D DR VIH VIL ROW t R AH t AS C t R AL t C AH COLUMN tAA t R AC t CA C tCLZ I/O VO H VO L OPEN V A L I D D AT A OPE N tOFF1 t O AC tORD OE V IH V IL tOFF2 DON'T CARE UNDEFINE D Elite Memory Technology Inc Publication Date : Dec. 2000 Revision : 1.2 12/15 EliteMT PACKING 40-LEAD SECTIONI D 40 21 b2 M10B416256A DIMENSIONS SOJ(400mil) 0.050" MAX . E1 E b 1 20 DETAIL "A" A2 A A1 e DETAIL "A" 0.024" MIN . R1 c 1 E2 X SECTIONII Symbol A A1 A2 b b2 c e D Dimension in mm Min Norm Max 3.250 3.510 3.760 2.080 2.790 REF 0.380 0.460 0.560 0.635 REF 0.180 0.250 0.360 1.270 BSC 25.91 26.040 26.290 Dimension in inch Symbol Dimension in mm Min Norm Max Min Norm Max 0.128 0.138 0.148 E 10.920 11.176 11.430 0.082 E1 10.030 10.160 10.290 0.110 REF E2 9.40 BSC 0.015 0.018 0.022 R1 0.760 0.890 1.020 0.025 REF b2 0.635 REF 0.007 0.010 0.014 1 0 10 0.050 BSC 1.02 1.025 1.035 e y1 1.270 BSC 0.381 Dimension in inch Min Norm Max 0.430 0.440 0.450 0.395 0.400 0.405 0.370 BSC 0.030 0.035 0.040 0.025 REF 0 10 0.050 BSC 0.015 Elite Memory Technology Inc Publication Date : Dec. 2000 Revision : 1.2 13/15 EliteMT PACKING 40 / 44-LEAD DIMENSIONS TSOP(II) DRAM(400mil) M10B416256A Symbol A A1 A2 b b1 c c1 D ZD E E1 L L1 e Dimension in mm Min 0.05 0.95 0.30 0.30 0.12 0.10 18.28 11.56 10.03 0.40 18.41 0.805 REF 11.76 10.16 0.59 0.80 REF 0.80 BSC O ~ 7 REF 11.96 10.29 0.69 0.35 1.00 Norm Max 1.20 0.15 1.05 0.45 0.40 0.21 0.16 18.54 Dimension in inch Min 0.002 0.037 0.012 0.012 0.005 0.004 0.720 0.455 0.395 0.016 0.725 0.0317 REF 0.463 0.400 0.023 0.031 REF 0.0315 BSC O ~ 7 REF 0.471 0.4 0.027 0.014 0.039 Norm Max 0.047 0.006 0.042 0.018 0.016 0.008 0.006 0.730 Elite Memory Technology Inc Publication Date : Dec. 2000 Revision : 1.2 14/15 EliteMT Important Notice All rights reserved. M10B416256A No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of EliteMT. The contents contained in this document are believed to be accurate at the time of publication. EliteMT assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by EliteMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express , implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of EliteMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. EliteMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Memory Technology Inc Publication Date : Dec. 2000 Revision : 1.2 15/15 |
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